Hardwareraspberry pimicrocontrollersrisc-v
Pico 2 costs $1 more than the original Pico and doubles the flash, with a choice of Arm or RISC-V cores
The upgrade is a drop-in for most projects, but the newer chip adds memory headroom, extra I/O state machines and a boot-time architecture switch.
Buying the original Pico over the Pico 2 now saves exactly one dollar, and that’s the whole price argument. The original is “available from $4.” The Pico 2 is “Available now from $5.” For a dollar you get twice the program storage, nearly twice the RAM, and a faster chip.
Both are bare boards. The wireless versions are a separate purchase: the Pico page lists the Pico W at $6, and the Pico 2 page reserves its 2.4GHz Wi-Fi and Bluetooth 5.2 for the “Raspberry Pi Pico 2 W only.” This comparison is the plain pair, $4 against $5.
The chip is the real change. The original runs the RP2040 with a “Dual-core Arm Cortex-M0+ processor” at up to 133 MHz. The new Raspberry Pi Pico 2 runs the RP2350 with “Dual Arm Cortex-M33 or dual Hazard3 RISC-V processors @ 150MHz.” Note the “or.” It’s two cores, one architecture at a time. Raspberry Pi’s launch post says the chip has “a pair of open-hardware Hazard3 RISC-V cores which can be substituted at boot time for the Cortex-M33 cores.” Nobody gets four cores running together.
Hazard3 is not Raspberry Pi’s design. Its repository sits under the Wren6991 account and is licensed Apache-2.0, and it describes a “3-stage RISC-V processor.” The launch post names Luke Wren as its developer. The repo says the RP2350 configuration “achieves 4.15 CoreMark/MHz.”
The board is meant to swap in. Raspberry Pi says Pico 2 is “form-factor and electrically compatible with the original Pico design,” and its product page calls it “Software- and hardware-compatible with Raspberry Pi Pico 1.” That’s the vendor’s claim, so a project that leans on odd timing tricks is worth testing on the new board before you ship a hundred of them.
| Pico | Pico 2 | |
|---|---|---|
| Starting price | $4 | $5 |
| Chip | RP2040 | RP2350 |
| Cores | Dual Arm Cortex-M0+ | Dual Arm Cortex-M33 or dual Hazard3 RISC-V |
| Top clock | 133 MHz | 150 MHz |
| SRAM | 264kB | 520KB |
| Flash | 2MB | 4MB |
| PIO state machines | 8 | 12 |
Every figure in the table comes from the two product pages. The launch post adds that SRAM is arranged in “ten concurrently accessible banks” and that the chip carries Arm TrustZone, signed boot support, 8KB of antifuse one-time-programmable memory, SHA-256 acceleration and a hardware true random number generator. I did not compare either board to a rival here. Other makers’ boards weren’t read for this piece, so the chart is old Pico against new.
What nobody says on either page is how many of the existing library of Pico projects will keep running unchanged on Hazard3. The Arm cores are the familiar default, and the boot-time switch exists for people who want to try the open design. Whether that crowd turns out to be large or small decides how much software you’ll find for the RISC-V side.
Expect the original to linger in kits only as long as leftover stock does, since a dollar is a small gap to defend.
Cheap at any clock speed.